1. Field of the Invention
The present invention generally relates to a semiconductor process, and more precisely to a method for a cross pitch doubled patterning process that does not require multiple films stacks or any planarization step.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a mask pattern. The mask pattern is then transferred to another layer. However, with the increasing miniaturization and the higher integration requirements of semiconductor devices, like memory devices (for example DRAM), the dimensions become finer and the dimensions of the masks need to become smaller as well.
Smaller holes sizes for contact printing masks are therefore obtained through double patterning with the use of multiple crossed patterns. Nevertheless, in order to obtain the desired final patterns, multiple stacks layers are used, thereby increasing the heights of the wholes structures leading to high aspect ratios. High aspect ratios are here a source of many variations that are to be avoided in order to achieve the most precise structures for obtain better performances in semiconductor devices.
In order to obtain the desired patterns, the actual processes using multiple layers also need more fabricating steps, and more steps in between, like planarization steps that are needed to achieve leveled semiconductor structures. All these steps make the whole process complex, long and expensive.
Therefore, how to reduce the number of layers needed in the process, so as to reduce the aspect ratio, as well as how to reduce the complexity of the process, so as to reduce the fabricating costs and time are important goals in this field.